Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

With increased clock domains in modern ASICs, clock-domain crossing (CDC) has become ubiquitous, indispensable, and essential. Of course, timing is always an issue. High clock speeds and delays in ...

This insatiable demand for data is what led to the need for JEDEC to introduce the JESD204 standard for a high-speed serial link between data converters and logic devices. The “B” revision of the ...

Synchronous interfaces involve a single clock domain and are relatively easy to design. However, at times, it is advantageous and necessary to have an asynchronous interface between peripherals for ...

Time-sensitive networks (TSN) in Ethernet are improving computer-based measurements from sub-microsecond to sub-nanosecond precision. By using message-based protocols that synchronize clocks, it is ...

The IEEE 1588 Precision Time Protocol enables precise time synchronization over the packet-based Ethernet network so that the time on a slave clock at one end of the network agrees with a master clock ...