EDN

Timing-driven Simulink FPGA synthesis

Simulink is popular among DSP designers, and FPGA vendors have taken note. These vendors have created blockset libraries that enable Simulink designs to be synthesized to an FPGA implementation. While ...
Electronic Design

FPGA Design Suite Builds In Timing Analysis With Native Support For SDC Format

With FPGAs pushing aside ASICs in many complex designs, the limits of traditional FPGA timing-analysis tools are being stressed to the breaking point. So if you want to use today's high-end FPGAs in ...
Design-Reuse

An FPGA primer for ASIC designers

With the advent of new technologies in IC design and complexity of the business models, chip designers may want to explore different choices available to them for implementation. ASICs have been the ...
Semiconductor Engineering

Rapid Timing Constraints Signoff With Automated Constraint Management

Signoff of a system on chip (SoC) or IP design has multiple aspects, but often timing closure is the most challenging. Early use of a static timing analysis (STA) tool is clearly important, and such a ...
EDN

Hi def video scaler ASIC development from FPGA

Consumers are buying ever larger numbers of liquid crystal displays (LCD), plasma and digital light processing (DLP) based systems. As digital displays continue to offer higher resolution capabilities ...
Design-Reuse

FPGAs: Embedded Apps : Designing an FPGA-based network communications device

Wilhelm Schreiber, Research and Development Engineer, Siemens Information and Communications Network Division, Munich, Germany, Thomas Zipper, Research and Development Engineer, Siemens Information ...