EDN

Power-aware FPGA design (Part 2)

FPGAs offer several embedded RAM blocks with unique sizes but variable aspect ratios. This feature opens the door for different cascading schemes. Fig 9 is an illustration of two alternatives that ...
EDN

Timing-driven Simulink FPGA synthesis

Simulink is popular among DSP designers, and FPGA vendors have taken note. These vendors have created blockset libraries that enable Simulink designs to be synthesized to an FPGA implementation. While ...
Design-Reuse

An FPGA primer for ASIC designers

With the advent of new technologies in IC design and complexity of the business models, chip designers may want to explore different choices available to them for implementation. ASICs have been the ...
Design-Reuse

FPGAs: Embedded Apps : Designing an FPGA-based network communications device

Wilhelm Schreiber, Research and Development Engineer, Siemens Information and Communications Network Division, Munich, Germany, Thomas Zipper, Research and Development Engineer, Siemens Information ...
Semiconductor Engineering

Rapid Timing Constraints Signoff With Automated Constraint Management

Signoff of a system on chip (SoC) or IP design has multiple aspects, but often timing closure is the most challenging. Early use of a static timing analysis (STA) tool is clearly important, and such a ...