Semiconductor Engineering

Making Cache Coherent SoC Design Easier with Ncore

As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris ...
EDN

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To ...
Electronic Design

AMD Takes EPYC Server CPUs to Another Level With 3D Cache

AMD is raising the bar in its battle against Intel in the data center with a new lineup of EPYC CPUs that use its 3D packaging technology to triple the L3 cache, giving them a significant hike in ...
Electronic Design

Server Processors Stack Up to 1.1 GB of 3D Cache

AMD is leveraging one of its latest families of EPYC server CPUs, code-named Genoa X, in-house to run the electronic design automation (EDA) tools it uses for product development. Based on TSMC's 5-nm ...