IEEE

Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

Abstract: Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology ...
IEEE

Design of Adder Circuits using GNRFETs in Ternary Logic

Abstract: This paper presents the design of ternary adder schematics with graphene nanoribbon field effect transistor (GNRFET). The adder circuits are developed by using the basic, universal and ...