Abstract: This paper presents a novel digital decision feedback equalizer (DFE) design that can relax the feedback timing constraints for analog-to-digital converter (ADC)-based high-speed wireline ...
Abstract: This letter presents the design and analysis of a wideband active vector-sum phase shifter in a 22-nm fully depleted silicon-on-insulator (FD-SOI) CMOS process. The phase shifter consists of ...
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